1. Field of the Invention
The present invention relates generally to a method for fabricating an interlayer conducting structure of an embedded circuitry. More particularly, according to the method of the present invention, there is no laser conformal mask formed prior to laminating the lamination plates. Instead, after the lamination plates are laminated, a laser boring process is conducted to form a via hole. In such a way, the risk of short circuit between different layers of lamination plates can be lowered without improving an interlayer offset value.
2. The Prior Arts
For obtaining a larger area for wiring, most current printed circuit boards (PCB) are multilayer PCBs. Circuitries of different layers of such a multilayer PCB are typically connected by via holes, blind holes, or buried holes. However, since the multilayer PCB is fabricated by laminating a plurality of lamination plates one by one, there is often an offset when aligning different lamination plates for laminating.
Referring to FIG. 1, it is a schematic diagram illustrating a conventional interlayer conducting structure. As shown in FIG. 1, a first circuitry 7 and a target point 5 are formed on a first lamination plate 1. A conformal mask pattern 9 is formed on a second circuitry 11 by executing a laser conformal mask processing thereon. The second lamination plate 3 is then laminated to the first lamination plate 1. Then, a laser boring process is executed to bore from the conformal mask 9 of the second lamination pate 3 through the second lamination plate 3 positioned on a stop pad of the first circuitry 7, thus forming a via hole 14 which ends at the stop pad of the first circuitry 7.
In this conventional technology of fabricating the interlayer conducting structure, the conformal mask is formed prior to laminating the first and second lamination plates. As such, any alignment offset between different lamination plates may lead to an offset between the conformal mask and the stop pad. Correspondingly, the via hole may be bored down through the second lamination plate 3, as shown in the A portion indicated in FIG. 1, which brings the risk of short circuit.